DAQ PCI-FRM01 Manual de usuario descargar pdf (Pagina 9)

Application Note (AN241)

PCI-FRM01 Register Level Application Guide

6. Interrupt Controller Usage

PCI-FRM01 has interrupt controller to handle the hardware interrupt for each I/O device.

When you use these interrupts, eliminating the use of polling overhead of the process can be reduced.

INTERRUPT

Interrupt Status Register (Read Only)B0h

Description

I/O Address

Offset

Function

B4h

B8h

BCh

Interrupt Status Clear (Write Only)

Interrupt Enable Register (Read/Write)

Interrupt Source Indicatior(Read Only)

INT_STA

INT_SEL

INT_EN

INT_SRC

To control 82C55 ports, first the mode have to set up through the control register. To all setup, most

significant bit(MSB) is set to high “1” and write to the control register. If the MSB is “0”, it will be

command of PORTC. (For more information, refer 82C55 manual)

When the first time power is applied, all ports will be the input and operation modes will be 0.

(1) INT_STA (Interrupt Status)

Indicates the current interrupt device that requires. To appear in the status register will have to make

the handle. When the write operation, status bits are cleared.

15 01234567891011121314

G Status S0

Reserved

INTERRUPT Status Register Bit Position & meaning

S14

Bit

Name

Description

Default Value

Reserved

‘0’

Reserved

‘0’

Reserved

‘0’

Reserved

‘0’

Reserved

‘0’

Reserved

‘0’

UART

Differential RS232C interface

‘0’

Reserved

‘0’

Reserved

‘0’

Reserved

‘0’

Reserved

‘0’

1 2 3 4 5 6 7 8 9 10 11 12 13 14

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DAQ PCI-FRM01 Manual de usuario Pagina 9

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